1. Field of the Invention
The present invention relates to bus architectures, and in particular, the interface between a bus actively transferring information and an add-on device inserted onto the bus.
2. Description of Related Art
The transfer of I/O data between devices in a computer system or between networks is typically carried out by a "local" or "network" bus, respectively. In many instances, a processor or bus controller controls the flow of information between devices. Each device on the bus may generate electrical signals representing address, data or interrupt information to the bus controller or other devices. These electrical signals on the bus are generated during time intervals or bus cycles synchronized by a bus clock. The number of bus cycles or transfers per second is used to classify the speed of a bus. For example, prior art busses may transfer information anywhere from 8 MHz to 25 MHz or higher. In a "network" bus, devices on the bus may be network interface devices which allow networks to transfer I/O data using an internetwork device such as a bridge, router or gateway.
When a device is added to a bus which is actively transferring information, the bus must accommodate the add-on device's consumption of power upon power up and introduction into the bus's active signal path. Typically, a bus is coupled to a backplane which is used to distribute power and connect devices to the bus. When a device, such as a circuit card, is inserted into the backplane, the insertion causes a surge of power consumption as the uncharged capacitances associated with the circuit card is shorted across the power supply. This power surge then affects the power supply to other devices on the backplane. Similar problems arise when the device comes into contact with the bus's active signal path. Likewise, uncharged capacitances associated with the inserted circuit card may disrupt the active signals on the bus.
In the prior art, limiting power disruption and degradation of bus signals during the insertion of add-on devices has been achieved by using Field Effect Transistors (FETs) on the backplane. However, these active circuits increase the cost and complexity of the bus interface. The use of FET devices requiring full source rating to handle 12 V without breakdown is expensive. It also requires the use of a higher power supply voltage to compensate for the voltage drop across the FET. Finally, present bus architectures require several bus cycles before the add-on device is configured and the bus is able to once again initiate transferring I/O data on the bus. Prior art buses required that the bus to be shut-down while the add-on device was inserted and required several bus cycles before the bus is brought back up.
Accordingly, it is desirable to produce an apparatus which prevents power and signal disruption during the inserting of the device onto the bus without using active circuitry and multiple bus cycles before the bus is able to transfer information.